The present application relates to a memory array, and more particularly, to a memory array comprising a local sense accelerator that can increase the speed of data transfer during read and write processes.
A conventional semiconductor memory array contains both global (or “main”) word and bit lines and local (or “sub”) word and bit lines. Read and write processes are performed by transferring data from the global bit lines to the local bit lines and vice versa. Access to the bit lines is facilitated by the word lines.
For example, FIG. 1 illustrates a conventional memory array 100. As shown in the diagram, the memory array 100 comprises differential local I/O lines, Lio and LioF, coupled to differential global I/O lines, Gio and GioF, by means of a plurality of transistors. For simplicity, only single differential pairs of global and local I/O lines are shown.
In operation, during a conventional read process, the local bit lines are pre-charged, meaning they contain a particular value. A column selection signal CSEL (see t0 in timing diagram of FIG. 2) is fired, which selects a specific word line. This causes the corresponding differential bit lines, Lio and LioF, to “mature,” meaning that one line discharges such that separation between Lio and LioF occurs (see Lio/LioF between t0 and t2 in timing diagram of FIG. 2). The lines have to reach a predetermined separation for a read process to begin (see t1 in timing diagram of FIG. 2). This separation frequently is about 300 mV. Therefore the memory array 100 also includes a current sense amplifier. This current sense amplifier detects a small current on the bit lines, converts the current to a voltage, and amplifies this voltage such that a stored value can be read from the memory. When the voltage reaches the minimum separation, the current sense amplifier fires a Read Enable signal (RdEn), which activates the transistors between the local and global lines, thereby allowing data transfer.
For a write process, values to be written to a local bit line are present on the global bit line. The CSEL signal (FIG. 2) is fired to select the appropriate word line, and the corresponding local bit lines begin to separate. When the current sense amplifier detects that the separation has reached approximately 300 mV, a write enable signal (WrEn) may be fired, which drives the global bit line values onto the local bit lines.
The timing of the CSEL signal and the corresponding separation of the bit lines for a read process is illustrated in FIG. 2. As shown in the diagram, the separation of the local bit lines is slow and gradual (see Lio/LioF at times t0, t1, and t2 in timing diagram of FIG. 2). Generally speaking, in order for fast read processes to occur, the voltage on the local bit lines should be as high as possible. In modern memory arrays, however, the circuit layout is often quite small, meaning that the current sense amplifier is also small and the amplification of the voltage is therefore limited.
Write processes are plagued by a similar set of problems. Additionally, an accepted phenomenon in the art is that as line length increases, so does line capacitance. In conventional memory arrays 100, the local bit lines are quite long, and therefore have a relatively large line capacitance. This phenomenon contributes in turn to the slow separation of the differential local bit lines, Lio and LioF (as seen in the Lio/LioF lines of FIG. 2), and thus causes a heavy loading problem when data is driven from the global bit lines, Gio and GioF, to the local bit lines, Lio and LioF.
In summary, characteristics of conventional memory design, such as the necessity for small sense amplifiers and the existence of line-based capacitances, induce inevitable problems with regards to read and write processes. It is therefore a priority in this field to design a system that can speed up the separation of the local bit lines.